In semiconductor devices, such as LSIs, various isolation techniques are used to electrically isolate elements disposed on semiconductor substrates. As the isolation method, for example, a method is used in which, using the p-n junction between p-well and n-well, an element in the p-well and an element in the n-well are isolated from each other. There is also a technique in which isolation is performed by forming a trench in a semiconductor substrate, such as shallow trench isolation (STI).
If isolation is insufficient, there is a possibility that the isolation breakdown voltage between adjacent elements may become low, resulting in occurrence of punch-through between the elements. The punch-through may cause leakage current and hinder reduction in power consumption and the like in semiconductor devices. Furthermore, as the distance between elements decreases with miniaturization of semiconductor devices, punch-through more easily occurs.
Accordingly, it is desirable to provide an isolation structure in which isolation breakdown voltage between elements may be sufficiently secured even if semiconductor devices become miniaturized. A technique regarding an isolation structure is described in Japanese Laid-Open Patent Publication No. 11-111639.